OSIRIS: automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip

This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is contemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communication conflicts over time. BA synthesis results for a network processor are discussed.