DocumentCode :
3498773
Title :
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs
Author :
Roloff, Sascha ; Hannig, Frank ; Teich, Jürgen
Author_Institution :
Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Erlangen, Germany
fYear :
2012
fDate :
Jan. 30 2012-Feb. 2 2012
Firstpage :
187
Lastpage :
192
Abstract :
The design and the programming of heterogeneous future MPSoCs including thousands of processor cores is a hard challenge. Means are necessary to program and simulate the dynamic behavior of such systems in order to dimension the hardware design and to verify the software functionality as well as performance goals. Cycle-accurate simulation of multiple parallel applications simultaneously running on different cores of the architecture would be much too slow and is not the desired level of detail. In this paper, we therefore present a novel high-level simulation approach which tackles the complexity and the heterogeneity of such systems and enables the investigation of a new computing paradigm called invasive computing. Here, the workload and its distribution are not known at compile-time but are highly dynamic and have to be adapted to the status (load, temperature, etc.) of the underlying architecture at run-time. We propose an approach for the modeling of tiled MPSoC architectures and the simulation of resource-aware programming concepts on these. This approach delivers important timing information about the parallel execution and also is taking into account the computational properties of possibly different types of cores.
Keywords :
invasive software; multiprocessing systems; parallel architectures; parallel programming; program verification; resource allocation; system-on-chip; approximate time functional simulation; compile time; computational properties; cycle accurate simulation; hardware design; heterogeneous MPSoC architecture; high-level simulation approach; invasive computing; multiple parallel applications; multiprocessor system-on-a-chip architecture; parallel execution; processor core; resource aware programming concept; software functionality verification; Computational modeling; Computer architecture; Programming; Reduced instruction set computing; Synchronization; Tiles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
ISSN :
2153-6961
Print_ISBN :
978-1-4673-0770-3
Type :
conf
DOI :
10.1109/ASPDAC.2012.6164943
Filename :
6164943
Link To Document :
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