Impact of polysilicon depletion in thin oxide MOS technology

Author

Schuegraf, Klaus F. ; King, C.-C. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng., California Univ., Berkeley, CA, USA

fYear

1993

fDate

1993

Firstpage

86

Lastpage

90

Abstract

Accurate characterization of thin oxide conduction current, breakdown, and MOSFET current require an accounting for the voltage drop due to the depletion of the polysilicon gate. The reduction of oxide thickness and polysilicon doping ascerbate this effect. Scaled n+/p+ dual gate CMOS technology incorporates both these trends, due to process integration constraints which limit the concentration of active dopants in polysilicon. The authors investigate effects of polysilicon depletion on the thin oxide MOS system.

Keywords

CMOS integrated circuits; insulated gate field effect transistors; MOSFET current; Si; band bending; breakdown; effects of polysilicon depletion; elemental semiconductor; reduction of oxide thickness; scaled n+/p+ dual gate CMOS; thin oxide MOS technology; thin oxide conduction current; voltage drop; Breakdown voltage; CMOS technology; Capacitance measurement; Capacitors; Conductivity; Doping; Implants; Impurities; MOSFET circuits; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-0978-2

Type

conf

DOI

10.1109/VTSA.1993.263633

Filename

263633