Title :
Hybrid parallel counters - domino and threshold logic
Author :
Townsend, Troy D. ; Celinski, Peter ; Al-Sarawi, Said F. ; Liebelt, Michael J.
Author_Institution :
Sch. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Abstract :
Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.
Keywords :
counting circuits; digital arithmetic; logic design; threshold logic; PPRT circuits; domino logic; hybrid parallel counters; partial product reduction tree circuits; threshold logic; Australia; CMOS logic circuits; Circuit testing; Counting circuits; Delay effects; Inverters; Logic devices; Logic testing; Pipelines; Very large scale integration;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339555
