• DocumentCode
    3498873
  • Title

    Hybrid parallel counters - domino and threshold logic

  • Author

    Townsend, Troy D. ; Celinski, Peter ; Al-Sarawi, Said F. ; Liebelt, Michael J.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
  • fYear
    2004
  • fDate
    19-20 Feb. 2004
  • Firstpage
    275
  • Lastpage
    276
  • Abstract
    Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.
  • Keywords
    counting circuits; digital arithmetic; logic design; threshold logic; PPRT circuits; domino logic; hybrid parallel counters; partial product reduction tree circuits; threshold logic; Australia; CMOS logic circuits; Circuit testing; Counting circuits; Delay effects; Inverters; Logic devices; Logic testing; Pipelines; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
  • Print_ISBN
    0-7695-2097-9
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2004.1339555
  • Filename
    1339555
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3498873