• DocumentCode
    3498897
  • Title

    A memory aware high level synthesis tool

  • Author

    Corre, Gwenolé ; Senn, Eric ; Julien, Nathalie ; Martin, Eric

  • Author_Institution
    L.E.S.T.E.R., South-Brittany Univ., Lorient Cedex, France
  • fYear
    2004
  • fDate
    19-20 Feb. 2004
  • Firstpage
    279
  • Lastpage
    280
  • Abstract
    We introduce a new approach to take into account the memory architecture and the memory mapping in high-level synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
  • Keywords
    high level synthesis; memory architecture; signal flow graphs; GAUT; data applications; high level synthesis tool; memory architecture; memory constraint graph; memory mapping; Algorithm design and analysis; Circuit synthesis; Constraint optimization; Design optimization; Flow graphs; High level synthesis; Memory architecture; Memory management; Signal synthesis; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
  • Print_ISBN
    0-7695-2097-9
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2004.1339557
  • Filename
    1339557