• DocumentCode
    3498901
  • Title

    An application classification guided cache tuning heuristic for multi-core architectures

  • Author

    Rawlins, Marisha ; Gordon-Ross, Ann

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
  • fYear
    2012
  • fDate
    Jan. 30 2012-Feb. 2 2012
  • Firstpage
    23
  • Lastpage
    28
  • Abstract
    Since multi-core architectures are becoming more popular, recent multi-core optimizations focus on energy consumption. We present a level one data cache tuning heuristic for a heterogeneous multi-core system, which classifies applications based on data sharing and cache behavior, and uses this classification to guide cache tuning and reduce the number of cores that need to be tuned. Results reveal average energy savings of 25% for 2-, 4-, 8-, and 16-core systems while searching only 1% of the design space.
  • Keywords
    cache storage; computer architecture; multiprocessing systems; application classification guided cache tuning heuristic; cache behavior; data sharing; heterogeneous multicore system; multicore architectures; multicore optimizations; Coherence; Energy consumption; Multicore processing; Optimization; Runtime; Tuners;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
  • Conference_Location
    Sydney, NSW
  • ISSN
    2153-6961
  • Print_ISBN
    978-1-4673-0770-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2012.6164950
  • Filename
    6164950