Post-silicon patching for verification/debugging with high-level models and programmable logic

Due to continuous increase of design complexity in SoC development, the time required for post-silicon verification and debugging keeps increasing especially for electrical errors and very corner case bugs (which happen in extreme rare but actual situations), and it is now understood that some sort of programmability in silicon is essential to reduce the time for post-silicon verification and debugging. In this paper, we discuss partial use of in-field programmability in control parts of circuits for post-silicon debugging processes for electrical errors and corner case logical bugs. Our method deals with RTL designs in FSMD (Finite State Machine with Datapath) by adding partially in-field programmability, called “patch logic”, in their control parts. If designs are given in high level like C-based designs, by using our high level synthesis techniques, they are first synthesized to include such in-field programmability in the control parts of the synthesized RTL automatically. With patch logic we can dynamically change the behaviors of circuits in such a way that state transition sequences as well as values of internal values are traced based on user requests. Our patch logic can also check if there is an electrical errors or not periodically. Assuming that electrical errors occur very infrequently, an error can be detected by comparing the equivalence on the results of duplicated computations. Through experiments we discuss the area, timing, and power overhead due to the patch logic and also show results on electrical error detection with duplicated computations.