An efficient test vector ordering method for low power testing

This paper presents a novel test vector ordering method for average power consumption minimization. The proposed method orders the test vectors taking into account the expected switching activity at the primary inputs and at a very small set of internal lines of the circuit under test. The computational time required by the proposed method is very small while the power reduction achieved is very close to the best, with respect to power reduction, most time-consuming method. Experimental results show that apart from average power reduction, the proposed method achieves significant peak power reduction too.