• DocumentCode
    3498951
  • Title

    Concurrent pseudo-exhaustive testing of combinational VLSI circuits

  • Author

    Shaer, B.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., UMD, USA
  • fYear
    2004
  • fDate
    19-20 Feb. 2004
  • Firstpage
    289
  • Lastpage
    290
  • Abstract
    Partitioning and concurrent pseudo-exhaustive test scheme has been proposed as a powerful solution to very large scale integrated (VLSI) testing problem. Pseudo-exhaustive test methodology provides effective, 100% fault coverage for all testable stuck-at faults. After partitioning the ISCAS´85 benchmark circuits, results were processed and studied to develop a procedure for concurrent testing. Tools written in C/C++ to process benchmark circuits and to produce sets of primary outputs and partitioned points that can be tested concurrently were developed.
  • Keywords
    VLSI; combinational circuits; logic testing; VLSI circuits; benchmark circuits; combinational circuits; concurrent testing; fault coverage; partitioning; pseudo-exhaustive testing; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Integrated circuit technology; Logic testing; Partitioning algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
  • Print_ISBN
    0-7695-2097-9
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2004.1339560
  • Filename
    1339560