DocumentCode
3498970
Title
CMOS analog programmable logic array
Author
Rajagopal, Chandrasekar ; Núñez-Aldana, Adrián
Author_Institution
Dept. of EECS, Syracuse Univ., NY, USA
fYear
2004
fDate
19-20 Feb. 2004
Firstpage
291
Lastpage
292
Abstract
In this paper, we present a methodology to design analog circuits and program the circuits using a digital bit stream to function like a desired complex circuit (ex. OTAs). The basic CMOS analog cells are synthesized from high-level circuit specifications into transistor net-lists using a two phase tuning process. The first phase uses a fast analog performance estimator to perform a global circuit sizing and the second phase involves Spice circuit simulations for a detail circuit sizing achieving high accuracy results. The synthesis environment relies on a genetic algorithm based heuristic method to search for a solution in a large design space.
Keywords
CMOS analogue integrated circuits; circuit simulation; integrated circuit design; programmable logic arrays; CMOS analog cells; CMOS analog programmable logic array; Spice circuit simulations; analog circuits design; analog performance estimator; digital bit stream; genetic algorithm; global circuit sizing; heuristic method; transistor net-lists; tuning process; Analog circuits; CMOS analog integrated circuits; CMOS logic circuits; CMOS process; Circuit optimization; Circuit simulation; Circuit synthesis; Design methodology; Phase estimation; Programmable logic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN
0-7695-2097-9
Type
conf
DOI
10.1109/ISVLSI.2004.1339561
Filename
1339561
Link To Document