DocumentCode :
3499015
Title :
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation
Author :
Gupta, Saket ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
fYear :
2012
fDate :
Jan. 30 2012-Feb. 2 2012
Firstpage :
271
Lastpage :
276
Abstract :
This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greater-than-nominal supply voltage, Vdd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, Vdd,n. In the second, the circuit is power-gated, enabling the BTI recovery phase. We demonstrate, both at the circuit and the architectural levels, that this approach can significantly mitigate aging for a small performance penalty.
Keywords :
ageing; delays; digital circuits; BTI mitigation; BTI recovery phase; GNOMO; aging mitigation; bias temperature instability; delay degradation mitigation scheme; digital circuits; greater-than-nominal supply voltage operation; Benchmark testing; Clocks; Degradation; Delay; Mathematical model; Optimized production technology; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
ISSN :
2153-6961
Print_ISBN :
978-1-4673-0770-3
Type :
conf
DOI :
10.1109/ASPDAC.2012.6164957
Filename :
6164957
Link To Document :
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