Autonomous buffer controller design for concurrent execution in block level pipelined dataflow

Author

Sadasivam, Magesh ; Hong, Sangjin

Author_Institution

Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA

fYear

2004

fDate

19-20 Feb. 2004

Firstpage

303

Lastpage

304

Abstract

This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.

Keywords

buffer storage; controllers; data flow computing; logic design; pipeline processing; reconfigurable architectures; autonomous buffer controller; block level pipelining; concurrent execution; concurrent processing; configurable controller structure; data flows; fine grain pipelining; memory centric coarse grain; orthogonal global information; system integration; Clocks; Concurrent computing; Control systems; Counting circuits; Delay; Hardware; Logic design; Pipeline processing; Reconfigurable logic; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on

Print_ISBN

0-7695-2097-9

Type

conf

DOI

10.1109/ISVLSI.2004.1339565

Filename

1339565

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3499038