Title :
Fast hot-carrier reliability diagnosis using macro-models
Author :
Jansz, W. ; Sun, W. ; Leblebici, Y. ; Kang, S.M.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana-Champaign, Urbana, IL, USA
Abstract :
A new macromodel-based reliability diagnosis program (iRULE) is presented for design of hot-carrier resistant VLSI circuits. iRULE detects first the potentially critical transistors by using netlist- and geometry-based rules and then determines the criticality of hot-carrier degradation in those transistors by using macro-models. The algorithmic complexity of iRULE is shown to be linear with respect to the number of logic gates. iRULE is capable of performing reliability diagnosis for CMOS circuits containing over one million transistors.
Keywords :
CMOS integrated circuits; VLSI; circuit CAD; circuit reliability; design for testability; hot carriers; knowledge based systems; CMOS circuits; algorithmic complexity; criticality of hot-carrier degradation; design; fast diagnosis; geometry-based rules; hot-carrier resistant VLSI circuits; iRULE; macromodel-based reliability diagnosis program; netlist-based rules; number of logic gates; potentially critical transistors; rule-based program; Analytical models; CMOS logic circuits; Circuit optimization; Circuit simulation; Degradation; Electron traps; Hot carriers; MOSFETs; Solid modeling; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263643