Probabilistic design in spintronic memory and logic circuit

Spin-transfer torque random access memory (STT-RAM) is a promising candidate for next-generation non-volatile memory technologies. It combines many attractive attributes such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. However, process variation continues to be a critical issue in the designs of STT-RAM and the derived spintronic logic. Besides the process-variation-induced persistent operation error, the non-persistent error that is incurred by the intrinsic thermal fluctuations of Magnetic Tunneling Junction (MTJ) devices significantly influences the spintronic circuit reliability. In this paper, we analyzed these two types of STT-RAM operation errors at both single cell and array levels. On the top of that, we quantitatively investigate the impacts of these errors on a nonvolatile spintronic flip-flop design. Some possible design techniques to reduce the operation error rate are also discussed. Our experimental results show that a statistical design technique must be adopted in spintronic memory and logic designs to achieve the desired operation reliability. We refer this technique as “probabilistic design”.