Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs

In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. Some of these TSVs become placement obstacles, i.e., they interfere with clock buffers and clock TSVs; while other TSVs become routing obstacles, i.e., clock wires cannot route through them. Thus, the key is to perform TSV-induced obstacle-aware 3D clock routing under the following goals: (1) clock TSVs and clock buffers are located while avoiding overlap with placement obstacles; (2) clock wires are routed while avoiding routing obstacles; and (3) clock skew and slew constraints are satisfied. Related experiments show that our TSV-obstacle-aware clock tree does not sacrifice wirelength or clock power too much while avoiding various TSV-induced obstacles.