Title :
Video signal processor (VSP) ULSIs for video data coding (in teleconferencing)
Author :
Enomoto, Tadayoshi ; Yamashina, Masakazu
Author_Institution :
Chuo Univ., Tokyo, Japan
Abstract :
The authors discuss progress achieved in the development of dedicated programmable real-time video signal processors (VSPs) for video data coding/decoding and of new technologies to improve VSP performance. A number of VSP LSIs are introduced, including a 14.5 MHz 16 bit Programmable Video Signal Processor (P-VSP), a 200 MHz 16 bit 0.8 mu m BiCMOS Super-high Speed Signal Processor (SSSP), a 250 MHz 16 bit 0.8 mu m BiCMOS Super-high-speed Video Signal processor (S-VSP) and finally a 300 MHz 16 bit 0.5 mu m BiCMOS Video Signal Parallel-Pipeline Processor (VSP3) sufficient for encoding full-CIF data at 30 frames per second.
Keywords :
BiCMOS integrated circuits; VLSI; codecs; digital signal processing chips; image coding; pipeline processing; teleconferencing; video signals; 0.5 micron; 0.8 micron; 14.5 MHz; 16 bit; 200 MHz; 250 MHz; 300 MHz; BiCMOS; DCT; Parallel-Pipeline Processor; Super-high Speed Signal Processor; coding/decoding; dedicated programmable; fast ALU; fast algorithms; multichip technology; real-time video signal processors; redundant binary logic; teleconferencing; video data coding; video encoder chip; video signal processor ULSI; Decoding; Discrete cosine transforms; Encoding; Large scale integration; Motion pictures; Pipelines; Signal processing; Teleconferencing; Ultra large scale integration; Videoconference;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263656
