DocumentCode
3499526
Title
High-speed, low-voltage design for high-performance static RAMs
Author
Sasaki, Katsuro
Author_Institution
Hitachi America, Ltd., Res. & Dev. Div., Terrytown, NY, USA
fYear
1993
fDate
1993
Firstpage
292
Lastpage
296
Abstract
High-speed, low-voltage design is key to attaining high-performance static RAMs. This paper describes high-density memory cell designs and high-speed, low-voltage circuit designs for CMOS and BiCMOS (ECL CMOS) static RAMs.
Keywords
BiCMOS integrated circuits; CMOS integrated circuits; SRAM chips; emitter-coupled logic; BiCMOS static RAM; CMOS static RAM; ECL CMOS; high speed design; high-density memory cell designs; low-voltage circuit designs; BiCMOS integrated circuits; CMOS memory circuits; CMOS technology; Circuit synthesis; Laboratories; Power supplies; Random access memory; Read-write memory; Research and development; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location
Taipei, Taiwan
ISSN
1524-766X
Print_ISBN
0-7803-0978-2
Type
conf
DOI
10.1109/VTSA.1993.263665
Filename
263665
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