Performance optimization of a high speed super self-aligned BiCMOS technology

Author

Liu, T.M. ; Chin, G.M. ; Morris, M.D. ; Jeon, D.Y. ; Johnson, R.W. ; Archer, V.D. ; Tarsia, M.J. ; Kim, H.H. ; Cerullo, M. ; Lee, K.F. ; Sung, J.M. ; Lau, K. ; Feuer, Mark D. ; Voshchenkov, A.M. ; Swartz, R.G.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

fYear

1993

fDate

1993

Firstpage

297

Lastpage

300

Abstract

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, f_max, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without compromise. The measured nominal CMOS gate delay with a gate length of 0.5 mu m is 47 psec at 5V and 54 psec at 3.3V.

Keywords

BiCMOS integrated circuits; integrated circuit technology; 0.5 micron; 3.3 V; 33.5 GHz; 47 ps; 5 V; 54 ps; CMOS ring oscillator; bipolar transistor power gain cutoff frequency; gate length; half-micron super self-aligned BiCMOS technology; high speed CMOS circuit operation; nominal CMOS gate delay; performance optimisation; process optimization; process parameters; BiCMOS integrated circuits; Bipolar transistors; CMOS memory circuits; CMOS process; CMOS technology; Capacitance; Cutoff frequency; Delay; MOS devices; Optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-0978-2

Type

conf

DOI

10.1109/VTSA.1993.263666

Filename

263666