Title :
A smart design methodology for advanced memories
Author :
Arimoto, Kazutami ; Asakura, Mikio ; Tsukude, Masaki ; Hidaka, Hideto ; Fujishima, Kazuyasu
Author_Institution :
LSI Lab., Mitsubishi Electric Corp., Hyogo, Japan
Abstract :
The authors propose a smart design methodology for advanced memories to reduce the turn around time for circuit revisions with no area penalty. This method was applied to the development of 16 Mb DRAM with double metal wiring. The turn around time can be reduced to 1/8 by 1500 gates of extra n-ch and p-ch transistors under the power line and the signal line. This design methodology is confirmed to be very effective.
Keywords :
CMOS integrated circuits; DRAM chips; VLSI; circuit layout; memory architecture; 16 Mbit; CMOS; DRAM; LSI; advanced memories; double metal wiring; smart design methodology; transistors; turn around time; Circuits; Design methodology; Fluctuations; Random access memory; Read-write memory; Signal generators; Silicon; Transistors; Voltage; Wiring;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263678
