Title :
A weighted reduced connectivity matrix partitioning algorithm [VLSI design]
Author :
Zhang, Weibiao ; Zhang, Ruili ; Hassoun, Marwan
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
M-way partitioning algorithms have many important applications in VLSI design. A heuristic Reduced Connectivity Matrix Partitioning (RCMP) algorithm can handle m-way partitioning with good time and space complexity. In this paper, we introduce a weighted RCMP (WRCMP) algorithm, which incorporates area constraints with performance objectives at the same time in order to extend the capability of RCMP. A program has been written and some experimental results are discussed. This modification would expand the application of the RCMP algorithm to area and performance constrained partitioning
Keywords :
VLSI; circuit layout CAD; graph theory; integrated circuit layout; matrix algebra; VLSI design; VLSI layout; area constrained partitioning; m-way partitioning algorithm; performance constrained partitioning; reduced connectivity matrix partitioning algorithm; weighted RCMP algorithm; Algorithm design and analysis; Application software; Buildings; Circuits; Computational modeling; History; Instruments; Partitioning algorithms; Simulated annealing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951415
