• DocumentCode
    3499909
  • Title

    Local oxidation process simulation in nanoscale MOS/CMOS structures

  • Author

    Andriukaitis, D. ; Anilionis, R.

  • Author_Institution
    Dept. of Electron. Eng., Kaunas Univ. of Technol.
  • fYear
    2006
  • fDate
    2-4 Oct. 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Problems of local oxidation, related with oxidation time, temperature, silicon oxide layer, patterned silicon nitride in MOS/CMOS structure was researched. During local oxidation of silicon most CMOS quality depends on gate channel shortening, diffusion region separation. Oxidation mathematical models are created using program SUPREM. It is determined, that most acceptable results are received when time t=12 min., temperature T=1000degC, SiO2 thickness = 4 nm., Si 3N4 thickness = 100 nm
  • Keywords
    CMOS integrated circuits; nanoelectronics; oxidation; silicon compounds; 100 nm; 1000 C; 12 mins; 4 nm; CMOS; SUPREM; Si3N4; SiO2; diffusion region separation; gate channel shortening; nanoscale MOS/CMOS structures; oxidation mathematical models; oxidation process simulation; oxidation time; patterned silicon nitride; silicon oxide layer; CMOS process; CMOS technology; Dielectrics; Fabrication; Isolation technology; MOSFETs; Oxidation; Production; Silicon; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Baltic Electronics Conference, 2006 International
  • Conference_Location
    Tallinn
  • ISSN
    1736-3705
  • Print_ISBN
    1-4244-0414-2
  • Electronic_ISBN
    1736-3705
  • Type

    conf

  • DOI
    10.1109/BEC.2006.311054
  • Filename
    4100275
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3499909