DocumentCode :
3500019
Title :
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints
Author :
Tsai, Shih-Heng ; Li, Man-Yu ; Huang, Chung-Yang
Author_Institution :
GIEE, Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2012
fDate :
Jan. 30 2012-Feb. 2 2012
Firstpage :
505
Lastpage :
510
Abstract :
Buffer Insertion has always been the most effective approach for timing optimization in VLSI designs. However, the emerging low-power design paradigm and the consideration of multiple operation modes and process corners (MMMC) have raised great challenges. Traditional dynamic-programming-based techniques are unable to cope with these challenges. In this paper, we develop a novel buffer insertion algorithm that utilizes a neighborhood restriction to simplify the constraint formulation and apply a semi-formal buffer refinement process to minimize buffer cost. The experimental results show that our tool can significantly reduce the buffer cost while meeting the MMMC timing constraints.
Keywords :
VLSI; dynamic programming; integrated circuit design; low-power electronics; timing; MMMC timing constraints; VLSI designs; constraint formulation; dynamic programming-based techniques; low-power design paradigm; multimode multicorner timing constraints; operation modes; process corners; semiformal buffer refinement process; semiformal min-cost buffer insertion technique; timing optimization; Bismuth; Capacitance; Delay; Merging; Resistance; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
ISSN :
2153-6961
Print_ISBN :
978-1-4673-0770-3
Type :
conf
DOI :
10.1109/ASPDAC.2012.6165005
Filename :
6165005
Link To Document :
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