A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS

Author

Niitsu, Kiichi ; Sakurai, Masato ; Harigai, Naohiro ; Hirabayashi, Daiki ; Yamaguchi, Takahiro J. ; Kobayashi, Haruo

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Kiryu, Japan

fYear

2012

fDate

Jan. 30 2012-Feb. 2 2012

Firstpage

553

Lastpage

554

Abstract

This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA), which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.

Keywords

CMOS analogue integrated circuits; amplifiers; clocks; integrated circuit design; timing jitter; CMOS design; CMOS fabrication; TDA; cascaded time difference amplifier; frequency 820 MHz; high-resolution on-chip timing jitter measurement circuit; operational speed; reference-free on-chip timing jitter measurement circuit; self-referenced clock; size 65 nm; timing jitter detection; Clocks; Frequency measurement; Latches; Semiconductor device measurement; System-on-a-chip; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific

Conference_Location

Sydney, NSW

ISSN

2153-6961

Print_ISBN

978-1-4673-0770-3

Type

conf

DOI

10.1109/ASPDAC.2012.6165014

Filename

6165014