DocumentCode :
3500241
Title :
Noise analysis of comparator performed sine-to-square conversion
Author :
Aaltonen, L. ; Saukoski, M. ; Teikari, I. ; Halonen, K.
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol.
fYear :
2006
fDate :
2-4 Oct. 2006
Firstpage :
1
Lastpage :
4
Abstract :
This paper describes a theoretical analysis of sine-to-square conversion when noise is included in the conversion process. The analysis is done for conversion performed by a comparator. As a result of the analysis, a simple method for calculating the spectrum of clock resulting from noisy conversion process is obtained. It will also be shown that the conversion process can easily lead to poor quality of the clock signal and that special attention should be paid when the clock is intended to be used for edge sensitive digital logic. To support the derived theory, simulation results will be presented
Keywords :
circuit noise; clocks; comparators (circuits); clock signal; comparator; edge sensitive digital logic; noise analysis; sine to square conversion; Circuit noise; Clocks; Demodulation; Electronic circuits; Jitter; Noise level; Performance analysis; Phase locked loops; Signal analysis; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Baltic Electronics Conference, 2006 International
Conference_Location :
Tallinn
ISSN :
1736-3705
Print_ISBN :
1-4244-0414-2
Electronic_ISBN :
1736-3705
Type :
conf
DOI :
10.1109/BEC.2006.311071
Filename :
4100292
Link To Document :
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