Title :
Proceedings of the 2006 7th International Symposium on Quality Electronic Design
Abstract :
The following topics are dealt with: variation-aware timing; high level design verification; robust device design; DSM timing issues; memory analysis; interconnect analysis; interconnect optimization; digital diagnosis techniques; back of line DFM; analog testing; elf-checking design; power aware design; memory management; IC package design; DSM interconnections; leakage analysis; system level design and reliability models
Keywords :
fault diagnosis; high level synthesis; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; integrated circuit testing; DSM interconnect; IC package design; analog self-checking design; digital diagnostic techniques; high level design verification; interconnect analysis; interconnect optimization; leakage analysis; memory analysis; memory management; power aware designs; reliability models; system level designs; variation-aware timing;
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.2
