Title :
CMOS scaling for the 22nm node and beyond: Device physics and technology
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. Technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed.
Keywords :
CMOS integrated circuits; system-on-chip; transistor circuits; CMOS scaling; advanced transistor architectures; device physics; system-on-chip; CMOS integrated circuits; Capacitance; Logic gates; Materials; Strain; System-on-a-chip; Transistors;
Conference_Titel :
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8493-5
DOI :
10.1109/VTSA.2011.5872206
