Statistically aware SRAM memory array design

Increasing process-parameter variations due to technology scaling to nanometer nodes have a significant impact on the circuit design flow. As shown repeatedly in previous work, a worst-case design approach is no longer feasible to guarantee a yielding design. Furthermore, the study of these process-parameter variations on the distributions of performance parameters has been done extensively in the past. However, this will not improve the circuit design unless the statistical information is considered during the optimization of the design. In this paper, we propose a method to minimize the leakage power of a SRAM cell while satisfying conflicting functionality and delay constraints, under these technology variations. Additionally, this method generates power-stability tradeoffs to optimize the circuit for a given yield at design time. Even at cell level, statistically aware design allows both minimal standby leakage power and minimal area