Title :
Ultra-fast noise immune CMOS threshold logic gates
Author_Institution :
RN2R, Rose Res. LLC, Dallas, TX, USA
Abstract :
This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support the theoretical claims. Finally, two methods for drastically reducing the dissipated power of such threshold gates down to <50%, and respectively <10% are also suggested
Keywords :
Boolean functions; CMOS logic circuits; VLSI; integrated circuit noise; logic gates; logic simulation; low-power electronics; threshold logic; Boolean form; CMOS threshold logic gates; VLSI; dissipated power; noise margins; nonlinear terms; simulation results; threshold function; ultra-fast logic gates; Books; CMOS integrated circuits; CMOS logic circuits; Circuit simulation; Helium; Integrated circuit noise; Inverters; Logic circuits; Logic gates; Noise reduction;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951456
