Design-patterning co-optimization of SRAM robustness for double patterning lithography

Double patterning lithography (DPL) provides an attractive optical lithography solution for 32nm and subsequent technology nodes. There are two primary DPL techniques: pitch-split double patterning (PSDP) and self-aligned double patterning (SADP), which can be implemented using a positive tone or a negative tone process. Each DPL implementation has a different impact on line space and linewidth variation, and by analyzing the impact of these different DPL options the best overall process flow can be achieved. This paper presents a comprehensive analysis and optimization framework that compares the layerwise impact of different DPL choices on SRAM robustness, density, and printability. It then performs a sizing optimization that accounts for increased variability due to DPL for each layer. Experimental results based on 45nm industrial models show that using the best DPL option for each layer, along with the sizing optimization presented, we can achieve single exposure robustness together with improved DPL printability at almost no overhead (less than 0.2% increase in write energy). Specifically, cell failure probability can be further reduced by 5X as compared to the single exposure failure probability, at the cost of increasing write energy by 6.3% and write delay by 2.5%.