Title :
Process development of a stacked chip module with TSV interconnection
Author :
Xiao Zhong ; Shenglin Ma ; Yunhui Zhu ; Yuan Bian ; Xin Sun ; Qinghu Cui ; Min Miao ; Jing Chen ; Yufeng Jin
Author_Institution :
Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China
Abstract :
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there´s no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a test run is carried out and a four-layer of chip module is demonstrated.
Keywords :
copper alloys; electroplating; integrated circuit interconnections; modules; three-dimensional integrated circuits; tin alloys; 3D integration process; Cu-Sn; TSV interconnection; VBR process; copper electroplating; microbumps; stacked chip module process development; via-backside-release process; Copper; Fabrication; Filling; Packaging; Through-silicon vias; Tin;
Conference_Titel :
Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4673-1682-8
Electronic_ISBN :
978-1-4673-1680-4
DOI :
10.1109/ICEPT-HDP.2012.6474556
