A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder

This paper presents a high speed decoder architecture for irregular structured low density parity check (LDPC) codes and its field programmable gate array (FPGA) implementation. Algorithm transformation and architectural level optimizations are employed to reduce the critical path. The enhanced semi-parallel architecture is easily scalable and reconfigurable for larger block sizes and can be well suited for achieving high decoding throughput. Based on the proposed architecture, a (10240, 5120) irregular structured LDPC decoder is implemented on Xilinx FPGA Virtex-4 VLX80, the FPGA implementation results show that the irregular LDPC decoder can achieve a maximum (information data) decoding throughput of 223 Mbps at 18 iterations.