Title :
Minimization of area in low-resistance MOS switches
Author :
Malik, Saqib Q. ; Geiger, Randall L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
Several different layout schemes that are useful for implementing low resistance switches with MOS transistors are discussed and characterized. A comparison of the area required for implementing a switch with a standard alternating bar approach is made with layouts using waffle structures, serpentine structures, and modified waffle structures. Analytical design equations for these non-conventional geometries are introduced. The comparisons show that in typical processes, area reductions of over 40% are readily achievable with the modified waffle structures
Keywords :
MOSFET; electric resistance; field effect transistor switches; minimisation; MOS transistors; MOSFET switches; area minimization; design equations; layout schemes; low resistance MOS switches; modified waffle structures; nonconventional geometries; serpentine structures; standard alternating bar approach; waffle structures; Contact resistance; Electric resistance; Equations; Geometry; MOSFETs; Resistors; Switches; Threshold voltage; Transconductance; Voltage control;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951473
