• DocumentCode
    3501071
  • Title

    Pessimism reduction in static timing analysis using interdependent setup and hold times

  • Author

    Salman, Emre ; Dasdan, Ali ; Taraporevala, Feroze ; Küçükçakar, Kayhan ; Friedman, Eby G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rochester Univ., NY
  • fYear
    2006
  • fDate
    27-29 March 2006
  • Lastpage
    164
  • Abstract
    A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools
  • Keywords
    logic design; sequential circuits; timing; hold times characterization; independent characterization; pessimism reduction; sequential circuits; setup times characterization; slack violations; static timing analysis; Clocks; Constraint optimization; Degradation; Delay effects; Frequency; Libraries; Optimization methods; Sequential circuits; Time factors; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-2523-7
  • Type

    conf

  • DOI
    10.1109/ISQED.2006.100
  • Filename
    1613130