Time-interleaved delta-sigma modulators using zero-insertion interpolation

One way to increase the conversion bandwidth of delta-sigma (ΔΣ) converters is to exploit the time-interleaving technique. In this paper, we propose a novel time-interleaving concept based on zero-insertion interpolation, which eliminates the high sampling rate multiplexer at the input stage, resulting in a significant simplification in the hardware complexity. In this approach, the input signal is only applied to the first channel whereas all the other channel inputs are fed with zeros at all times. The low-pass filter at the output of the modulator serves two purposes; (i) it rejects the spectral replicas of the input signal arising form zero-insertion upsampling, (ii) it attenuates the out-of-band quantization noise. The effects of input sampling clock jitter are also studied in this paper