DocumentCode :
3501222
Title :
SRAM local bit line access failure analyses
Author :
Elakkumanan, Praveen ; Kuang, Jente B. ; Nowka, Kevin ; Sridhar, Ramalingam ; Kanj, Rouwaida ; Nassif, Sani
fYear :
2006
fDate :
27-29 March 2006
Lastpage :
209
Abstract :
Due to the increasing process parameter variations and bitline capacitance, design of fast, reliable and robust read/write circuits for nanoscale SRAMs is a challenge. In this paper, we have investigated the effect of threshold voltage variations on the stability of read and write access schemes in SRAM designs. We considered three small signals read out and two write schemes to establish the SRAM local bitline failure trends and behavior under aggressive timing constraints and in the presence of process variations. The critical transistors in both the memory cell and the sense circuits are determined using corner analyses. Detailed simulation analyses are then performed by randomly varying the threshold voltages of these critical transistors, and the failing probabilities and points are then determined. Observations and conclusions on the failure trends of both the read and write operations are presented
Keywords :
SRAM chips; failure analysis; integrated circuit testing; logic testing; bit line access; bitline capacitance; critical transistors; failing probabilities; failure analysis; nanoscale SRAM; process variations; read access scheme; threshold voltage variations; timing constraints; write access scheme; Analytical models; Capacitance; Circuit simulation; Circuit stability; Failure analysis; Random access memory; Robustness; Signal processing; Threshold voltage; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
Type :
conf
DOI :
10.1109/ISQED.2006.120
Filename :
1613137
Link To Document :
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