Title :
Impact of NBTI on SRAM read stability and design for reliability
Author :
Kumar, Sanjay V. ; Kim, Chris H. ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN
Abstract :
Negative bias temperature instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in static noise margin (SNM) which is a measure of the read stability of the 6-T SRAM cell has been estimated using reaction-diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique
Keywords :
SRAM chips; integrated circuit design; integrated circuit reliability; logic design; nanoelectronics; 100 nm; 70 nm; PMOS devices; SRAM read stability; circuit reliability; data flipping; design for reliability; nanometer scale devices; negative bias temperature instability; reaction-diffusion model; static noise margin; transistor threshold voltage; Circuit stability; Degradation; Digital circuits; MOS devices; Nanoscale devices; Negative bias temperature instability; Niobium compounds; Random access memory; Threshold voltage; Titanium compounds; Cache; Negative Bias Temperature Instability (NBTI); Reaction-Diffusion (R-D) Model.; SRAM; Static Noise Margin (SNM);
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.73
