Title :
A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology
Author :
Bastani, Ali ; Zukowski, Charles A.
Author_Institution :
Columbia Univ., Vancouver, BC
Abstract :
In this paper, we investigate the use of monotonic static CMOS logic within a high performance carry look-ahead adder (CLA) in the context of a 65nm technology with significant leakage. The goal is a good compromise between speed, power, and noise immunity. We compare the monotonic static CMOS 64b CLA with domino and static CMOS adders with respect to speed and power consumption, using a predictive dual gate oxide 65nm technology with significant gate leakage. The comparison shows that monotonic-static CMOS is a potentially useful alternative in such applications. Compared to domino and static CMOS, it can provide advantages in evaluation speed and static power for a set of nominal gates sizes
Keywords :
CMOS logic circuits; adders; leakage currents; 64 bit; 65 nm; CMOS adder; CMOS logic; carry look-ahead adder; gate leakage; monotonic static CMOS; power consumption; predictive dual gate oxide; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Circuit synthesis; Clocks; Energy consumption; Leakage current; Logic circuits; Logic gates;
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.12
