• DocumentCode
    3501557
  • Title

    CMOS nanoelectronics at the time of diversifications

  • Author

    Deleonibus, Simon

  • Author_Institution
    MINATEC, CEA-LETI, Grenoble, France
  • fYear
    2011
  • fDate
    25-27 April 2011
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Nanoelectronics linear scaling appeals for new 3D integration schemes enabling to continue Moore´s law. Unique opportunities exist to increase the devices performances, system complexity and reduce power consumption of mobile, handheld objects. Devices other than CMOS can be co-integrated with CMOS to interface the outside Multiphysics world (MEMS, sensors and actuators, RF devices, power devices,...) allowing new functionalities. 3D Wafer Level Packaging and System on a Wafer pave the way to these new routes.
  • Keywords
    CMOS integrated circuits; nanoelectronics; 3D integration schemes; 3D wafer level packaging; CMOS nanoelectronics; Moore´s law; linear scaling; mobile handheld objects; multiphysics world; power consumption; system complexity; CMOS integrated circuits; Copper; Logic gates; Nanoelectronics; Nanowires; Silicon; Three dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    978-1-4244-8493-5
  • Type

    conf

  • DOI
    10.1109/VTSA.2011.5872258
  • Filename
    5872258