Title :
An assessment of patterning options for 15nm half-pitch
Author :
Bencher, Christopher
Author_Institution :
Appl. Mater. Inc., Santa Clara, CA, USA
Abstract :
Despite the challenges in scaling below 20nm half-pitch, several technology roadmaps show applications with 15nm half-pitch patterning requirements as early as 2014~2015. These include 15nm node NAND wordlines, and possibly active/STI and bitline; as well as 15nm node fin patterning for Logic, if the FinFET technology is adopted. This timing, however, is well in advance of the EUV manufacturing tool roadmaps for 3rd or 4th generation EUV scanners; the current 15nm proof of concept used a laboratory configuration combining high numerical aperture (>;0.3), off-axis illumination from a synchrotron light-source, and pseudo-phase-shift-masks. Therefore, the industry will most likely need to turn to process integration schemes and apply density multiplication techniques to achieve the 15nm half-pitch from existing manufacturing technologies.
Keywords :
MOSFET; nanopatterning; ultraviolet lithography; EUV manufacturing tool roadmaps; EUV scanners; FinFET technology; NAND wordlines; density multiplication; half-pitch patterning; node fin patterning; pseudo-phase-shift-masks; size 15 nm; synchrotron light source; Chemicals; Extraterrestrial measurements; Laminates; Lithography; Resists; Self-assembly;
Conference_Titel :
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8493-5
DOI :
10.1109/VTSA.2011.5872262