Cost effective scaling to 22nm and below technology nodes

For decades, Moore´s law transistor cost scaling created a vibrant ecosystem of foundries, fabless design houses, IDMs, and suppliers. Each of these parties shared in the abundant economic benefits of the transistor cost scaling enabled by Moore´s law. This led to specialization within each layer and vertical segment of the supply chain wherein rigid technical interfaces allowed uni-dimensional technology trajectories to thrive. As we approach the challenges of achieving economic scaling at 22nm and beyond, we are confronted with a new set of challenges that will require tighter integration along historically rigid interfaces. This environment sets the stage for the pendulum to swing toward technologies that take advantage of tighter coupling between layout architectures and process capabilities, and between process control needs and product sensitivities. Process variability is creating daunting challenges for achieving predictable process and product times-to-market with economically acceptable yield levels. The sources of variability are magnified when aggressively scaling technology nodes based on the same fundamental device architectures, processes, and layout design styles. The introduction of a Metal Gate/High-K (MGHK) stack at the 32/28nm technology node will help to reduce random variations due to random dopant fluctuations (RDF), but only for one or two generations. For the 15 nm technology nodes and beyond, the only hope to limit RDF is to adopt novel device architectures that would reduce the dopant concentration in the channel (FinFET or Fully Depleted SOI). In addition to the RDF and other random fluctuations due to line edge roughness, etc., aggressive scaling has increased the layout dependent systematic variability primarily due to resolution limitations and the application of stressors in modern device architectures. Complex DFM flows have been proposed to model such layout dependent effects, however, the lack of accuracy with these modeling atte- - mpts has marred their adoption. We can show, however, that there is hope for minimizing these systematic variations with a pro-active DFM approach that requires design and process to be developed based on a set of pre-characterized circuit elements (templates). It is important to note that if left unchecked, these systematic variations will have a prohibitive impact on 22nm designs. The inability to scale the wavelength of the light source for lithography has led to an increase of process and design costs. In particular, the lack of progress in extreme ultraviolet lithography (EUVL) sets the need to define 22nm technology node using expensive double patterning technologies (DPT). We will examine the lithographic limitations that will be encountered in future technology nodes, including 22nm, and propose a design methodology to overcome these challenges. Thus taking the next step in Moore´s law with the application of smarter and more efficient circuit, layout, and lithography co-design techniques that can provide high density and increased yields at a sustainable cost. The key enabler of this methodology is the creation of a regular design fabric onto which one can efficiently map the selected templates using a limited number of printability-friendly layout patterns. The co-optimization of circuit, layout, and process is achieved by co-developing circuit functions, layout pattern library and lithography solutions. This solution replaces design rules for logic with a rigorously characterized set of layout Templates. We will demonstrate that this methodology will enable future technology nodes that utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choice of regular design fabrics and their implications on design metrics, yields and cost; show that the selection of circuit topologies can be mapped efficiently to the choice of regular design fabric; and compare lithography solutions such as DPT, direct