Title :
Physical IP and advanced SOI design for 22nm SOI technology
Author :
Pelloie, Jean-Luc ; Laabidi, Selma ; Charafeddine, Kenza ; Laplanche, Yves
Author_Institution :
ARM Grenoble Design Center, Grenoble, France
Abstract :
The 22nm CMOS technology node is currently under development at the major semiconductor companies. While the process is being developed and the associated design rules qualified it is important to set in parallel the design infrastructure to enable early circuit design. This paper shows how this has been accomplished through the design of a test chip including a circuit demonstrator.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit testing; silicon-on-insulator; CMOS technology node; SOI technology; advanced SOI design; associated design rules; circuit demonstrator; circuit design; design infrastructure; physical IP; semiconductor company; size 22 nm; test chip; Capacitance; History; Libraries; Power demand; Routing; System-on-a-chip; Timing;
Conference_Titel :
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8493-5
DOI :
10.1109/VTSA.2011.5872266
