A low input, low-power dissipation CMOS ADC

Author

Wang, Biye ; He, Lili ; Jones, Morris

Author_Institution

Dept. of Electr. Eng., San Jose State Univ., CA

fYear

2006

fDate

27-29 March 2006

Lastpage

386

Abstract

This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.25 micron; 0.75 to 1.75 V; 0.795 mm; 1.023 mm; 195 kHz; 2.5 V; 78.3 mW; 8 bit; CMOS technology; low-power dissipation; pipelined CMOS ADC; CMOS technology; Calibration; Circuits; Frequency; MOSFETs; Pipelines; Power dissipation; Quantization; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-2523-7

Type

conf

DOI

10.1109/ISQED.2006.11

Filename

1613167

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3501770