DocumentCode
3501782
Title
New design method of the 3-Dimensional vertical stacked FG type NAND cell arrays without the interference effect
Author
Seo, Moon-Sik ; Endoh, Tetsuo
Author_Institution
Center for Interdiscipl. Res., Tohoku Univ., Sendai, Japan
fYear
2011
fDate
25-27 April 2011
Firstpage
1
Lastpage
2
Abstract
We intensively investigated the interference effect by direct or indirect coupling path with neighboring cells of the 3-Dimensional (3-D) vertical Floating Gate (FG) type NAND cell arrays. Above all, we proposed the optimum 3-D vertical FG type NAND cell array structure to fully suppress the interference effects.
Keywords
NAND circuits; flash memories; integrated circuit design; interference suppression; 3-dimensional vertical stacked FG type NAND cell arrays; 3D vertical floating gate type NAND cell arrays; NAND flash memory cell arrays; direct coupling path; indirect coupling path; interference effect suppression; Capacitance; Couplings; Flash memory; Interference; Logic gates; Solid modeling; Very large scale integration; 3-D vertical cell; FG type NAND; Interference effect;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-8493-5
Type
conf
DOI
10.1109/VTSA.2011.5872270
Filename
5872270
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