Title :
Junction-less stackable SONOS memory realized on vertical-Si-nanowire for 3-D application
Author :
Sun, Y. ; Yu, H.Y. ; Singh, N. ; Le, T.T. ; Gnani, E. ; Baccarani, G. ; Leong, K.C. ; Lo, G.Q. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., A*STAR, Singapore, Singapore
Abstract :
This work demonstrates a new type of SONOS memory in which there are no junctions. These junction-less (JL) devices are realized on vertical Si nanowire gate all-around structure with channel dimension down to 20nm and have comparable electrical characteristics (SS <; 70mV/dec, leakage current <;1×10-12 A and a memory window of 3.2V with 1ms P/E) with the junction based wire SONOS. Being free of junctions, the process complexity is significantly reduced and this device becomes a suitable platform for vertically stacked ultra high density memory application.
Keywords :
integrated memory circuits; leakage currents; nanowires; silicon; Si; channel dimension; junction-less stackable SONOS memory; leakage current; memory window; process complexity; size 20 nm; vertical Si nanowire gate; vertically stacked ultra high density memory; voltage 3.2 V; Doping; Implants; Junctions; Logic gates; SONOS devices; Tunneling; Wires;
Conference_Titel :
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8493-5
DOI :
10.1109/VTSA.2011.5872271
