A novel program disturb mechanism through erase gate in a 110nm sidewall split-gate Flash memory cell

In this paper, we present a new erase gate disturb mechanism during programming of selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell sharing the same erase gate as the selected cell. The disturb is due to electron-loss from floating gate to erase gate caused by low-field Fowler-Norheim (F-N) tunneling. We proposed a method that adds extra bias voltages at unselected control gates to suppress EG disturb without changing process or losing cell erasing performance. The measured result shows that 2.5V on the control gate of the unselected cell can reduce erase gate disturb efficiently.