Yield enhancement methodology for CMOS standard cells

Author

Epinat, Arnaud ; Vijayaraghavan, N. ; Sautier, Matthieu ; Callen, Olivier ; Fabre, Sébastien ; Ross, Ryan ; Simon, Paul ; Wilson, Robin

Author_Institution

STMicroelectronics, Crolles

fYear

2006

fDate

27-29 March 2006

Lastpage

502

Abstract

In order to maximize the yield of random logic in today´s advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples

Keywords

CMOS integrated circuits; failure analysis; integrated circuit design; integrated circuit testing; integrated circuit yield; CMOS standard cells; data collection; design debug; failure analysis; failure location; industrial test; random logic; test vehicle approach; volume analysis; yield enhancement methodology; CMOS logic circuits; CMOS process; CMOS technology; Failure analysis; Life testing; Logic design; Logic testing; Random access memory; Standards development; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-2523-7

Type

conf

DOI

10.1109/ISQED.2006.147

Filename

1613185