Abstract :
Traditionally, IC designers have been able to define "Quality of Results" (QoR) primarily in terms of functionality, area, speed, and power. Hardly a backward glance was given to what manufacturers would do once the designs were handed off to them. Today, manufacturability has clearly joining the ranks of QoR. This is particularly true for technology nodes at 65 nanometers (nm) and below. Yield loss mechanisms, both functional and parametric, have become dependant on the design and increasingly, as geometries continue to shrink to 45nm and below, must be addressed from design to lithography to process. In this talk, we will examine some solutions being used to ensure quality in this area of concern. Topics include incorporating yield-rated cells and probabilistic methods such as statistical timing analysis to address yield losses early in the design. Test is being used for diagnosis. Routing optimization techniques such as minimizing critical areas for shorts and open circuits, wire-spreading, redundant vias and dummy metal fills improve manufacturability for metal layers. Further down the tool chain, resolution enhancement techniques (RET) used in mask synthesis addresses lithography, improving printability and hence yield. Manufacturing process knowledge is becoming increasingly important in design to enable effective yield modeling. TCAD models are making their way into manufacturing, helping, for example, to simulate statistical variations of electrical parameters as a function of process parameters.
