Title :
Improved switching activity estimation for behavioral and gate level designs
Author :
Wright, Ronnie L. ; Shanblatt, Michael A.
Author_Institution :
DCS Corp., Alexandria, VA, USA
Abstract :
A technique is presented for accurately computing the switching activity of digital circuits described-by behavioral- and gate-level designs. Accurate switching activity estimation for high-level designs provides early warning of potential power problems, supporting design flexibility and a reduction of time and cost. The technique uses a behavioral VHDL specification or gate-level netlist as input. For a variety of combinational benchmark circuits, assuming the zero-delay model and uncorrelated primary inputs, the approach has been tested and compared with the Berkeley SIS power estimator. The proposed technique has been implemented in a program called,the behavioral level activity and power estimator (BLAPE). Experimental results demonstrate a saving in time with an average error less than 1.00%
Keywords :
VLSI; circuit optimisation; combinational circuits; delay estimation; hardware description languages; high level synthesis; integrated circuit design; low-power electronics; BLAPE; IC design; VHDL; VLSI; behavioral level activity and power estimator; behavioral level designs; combinational benchmark circuits; design flexibility; design optimization; gate level designs; high-level designs; low power design; switching activity estimation; uncorrelated primary inputs; zero-delay model; Capacitance; Circuit testing; Equations; Hardware design languages; Input variables; Intellectual property; Logic; Portable computers; Probability; Switching circuits;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951613
