Failure analysis of the contamination on the pins of the SOT packages

Small Outline Transistor (SOT) package is a small, inexpensive, surface mount plastic-molded package, commonly used in consumer electronics. During the process of SOT packaging, the contamination is occasionally found on some SOT leads, which prevents the soldering in the assembly process. In this paper, an integrated failure analysis to solve the contamination problem is present. The surface topography and the elemental composition of the contaminant are examined by optical microscopy, SEM/EDX techniques. The structures of the organic contaminants are characterized by FTIR. After a careful analysis on the materials used in each step of packaging process and an absorption spectrum comparison with the contaminants, the possible source of the contamination is determined. To recur the contamination, a series simulation experiments were conducted and the produced substances on the lead surface were compared with the original contaminant. Infrared analysis results show that the structure of the new compounds from simulation experiments is similar to that of the original organic contaminant. The organic contamination is caused by the unexpected chemical deposition of the softening fluids with electroplating fluid on the lead frame surface, which left on the packaged chip lead surface in electroplating flow. The contamination could be eliminated by regulating the packaging processes and related parameters and conditions.