Analysis of process variation´s effect on SRAM´s read stability

Author

Chung-Kuan Tsai ; Marek-Sadowska, M.

Author_Institution

California Univ., Santa Barbara, CA

fYear

2006

fDate

27-29 March 2006

Lastpage

610

Abstract

In this paper we analyze the effect of manufacturing process variations on the SRAM stability in the read operation. We analyze the SRAM´s read operation and the DC voltage-transfer characteristics (VTCs). Based on the VTCs, we define the read margin to characterize the SRAM cell´s read stability. We calculate the read margin based on the transistor´s current model using the BSIM3v3 model. Experimental results show that the read margin accurately captures the SRAM´s read stability as a function of the transistors threshold voltage and the power supply voltage variations

Keywords

SRAM chips; circuit stability; integrated circuit design; logic design; BSIM3v3 model; DC voltage-transfer characteristics; SRAM read operation; SRAM stability; manufacturing process variations; power supply voltage variations; transistor current model; transistors threshold voltage; CMOS technology; Failure analysis; Manufacturing processes; Nanoscale devices; Power supplies; Random access memory; SRAM chips; Semiconductor device modeling; Stability analysis; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-2523-7

Type

conf

DOI

10.1109/ISQED.2006.26

Filename

1613204